The invention is an improvement in dynamic random access memories basically of the kind described in U.S. Pat. No. 4,012,757 which issued to J. T. Koo on Mar. 15, 1977, and includes a method for making such an improved memory.
The Koo memory is a random access memory which uses an array of storage cells each of which includes a single transistor control element merged with a single capacitive storage element. The array of storage cells is organized as a two-dimensional matrix of rows and columns. Elements of each row are coupled by way of the controls or gates of the transistors which comprise the row. This coupling conductor is generally termed the word line. Elements of each column are coupled by way of the source regions of the transistors which comprise the column. This coupling conductor is generally termed the bit line. In this memory the bulk of the semiconductive chip typically is p-type and a diffused n-type region which extends the length of the array serves as a merged bit line and the source regions of all the transistors in a particular column. Sensing is also accomplished by way of the bit lines, and, accordingly, this line is sometimes also called the sense line.
Each transistor includes its localized-type channel region, which is overlaid with its suitably insulated gate or control, and a virtual drain region which is overlaid with a suitably insulated electrode. In operation this electrode is held at a suitable bias potential which maintains localized inversion of the underlying region so that it effectively behaves as an n-type region and as a virtual drain zone. Similarly, control signals applied by way of the word line to the gate of a selected transistor cause localized inversion of the associated channel region to provide conduction between the source and drain regions of the selected transistor.
Moreover, each of the drain regions serves as one plate of the capacitive storage element and the other plate is provided by the overlying electrode. Accordingly, in each cell the drain region of the transistor is merged with one plate of the capacitive storage element. The total storage capacitance essentially comprises two components, the larger is the capacitance associated with the inverted layer and the overlying storage electrode, the smaller is the capacitance associated with the inverted layer and the underlying portion of the chip.
The mergers of the bit line and source regions and of the drain regions and capacitive elements are intended to increase the compactness of the cell to permit increased density of the cells on a single chip and a larger number of cells in a single chip. For reasons well known it is advantageous to maximize the number of cells in a chip consistent with economic manufacture of the chip.
Further to conserve space and thereby make possible increased cell density, the cells are physically arranged in pairs in an interleaved pattern to permit adjacent transistors of a pair in a common column to share a common source zone and the transistors in a common row to share a common conductive layer for the gate electrode. Electrical isolation of adjacent pair of cells from all other pairs is achieved by surrounding each pair by a passive region of more heavily doped p-type material which resists inversion in operation.
It is to be understood that the terms "row" and "column," as used herein, could be interchanged since they are purely arbitrary. Similarly, it is to be understood that whether a region acts as a source or drain depends on the conductivity type of the silicon chip and the polarity of the applied potentials.
An object of the present invention is to provide an improved memory, particularly by increasing its packing density.
Another object is a convenient process for making such a memory.